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Description: fft在dspbuilder下产生VHDL源码及其测试激励文件的matlab模型,在modelsim下仿真通过-fft in dspbuilder under VHDL source code and test incentives document matl ab model, the simulation under through modelsim
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Size: 7812 |
Author: zqh |
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Description: FFT算法的VHDL语言实现
可在Modelsim上运行和调试 -FFT algorithm VHDL in the operation and Modelsim Debugging
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Size: 29769 |
Author: 紫蓝 |
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Description: FPGA加密的方法,对于那些需要加密自己的vhdl源代码的人来说,很有用-FPGA encryption methods for those who need to encrypt their VHDL source code in a way, very useful
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Size: 187392 |
Author: 陶伟炯 |
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Description: VHDL 关于2DFFT设计程序
u scinode1 ∼ scinode9.vhd: Every SCI node RTL vhdl code. The details can be
seen in the following section.
u 2dfft.vhd: The top module includes these scinodes and form a 3x3 SCI Torus
network, and it support these sub-modules scinode1∼ scinode9 reset and clk
and global_cnt signals to synchronous the sub-modules to simplify the overall
design.
u proj2.wfc: VSS simulation result that is the same as the ModelSim simulation
result.
u Pro2_2.wfc: VSS simulation result of another test pattern can’t cause overflow
situation.-VHDL design procedures on 2DFFT u scinode1
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Size: 783360 |
Author: 李成 |
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Description: IP核应用,详细的介绍了关于FPGA中IP核的应用-IP core application, a detailed presentation on the application of FPGA in the IP core ,,,,,,
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Size: 705536 |
Author: 洪依 |
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Description: this is a code in VHDL for FFt and its inverse. also the programs are given in matlab
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Size: 29696 |
Author: mimi |
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Description: This book is ERICSSON documentation "FFT, REALIZATION AND IMPLEMENTATION IN FPGA".
Book includes some theoretical information about FFT Radix-2 and Radix-4, and also VHDL and Matlab code.
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Size: 297984 |
Author: Anta |
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Description: 给出了16位浮点FFT的算法代码及相关资料-Given a 16-bit floating-point FFT algorithm code and related information
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Size: 418816 |
Author: 陈少飞 |
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Description: FFT在高动态扩频信号捕获过程中的应用方法,基于此,可以相应地进行程序设计-FFT in the high dynamic spread-spectrum signal acquisition in the process of application method, based on this, you can design the appropriate conduct of the proceedings
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Size: 58368 |
Author: 党秀 |
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Description: 该工程实现了一个64点FFT,verilog编写,采用R4SDF结构,通过Modelsim功能仿真,压缩包里有rtl代码,dc脚本,输出报告。-The project implements a 64-point FFT, verilog compiled by R4SDF structure, through the Modelsim functional simulation, compression bag with rtl code, dc script, the output report.
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Size: 1255424 |
Author: ShuChen |
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Description: 用FPGA编程实现fft算法,在maxplus2环境下实现,好用-Fft algorithm with FPGA programming, in maxplus2 environment to achieve, easy to use! !
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Size: 2048 |
Author: 昶 |
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Description:
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Size: 209920 |
Author: Nagendran |
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Description: FFT蝶形运算单元程序,可用于OFDM,以及任何相关数字信号处理的设计中-FFT butterfly processor program can be used in OFDM, as well as any relevant design of digital signal processing
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Size: 1024 |
Author: 姚兴波 |
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Description: it is the document which will help in implementing vhdl fft
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Size: 362496 |
Author: tinku |
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Description: fft document in vhdl
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Size: 297984 |
Author: jim |
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Description: This a code for FFT in VHDL, Verilog & C
Source: OpenCores.org-This is a code for FFT in VHDL, Verilog & C
Source: OpenCores.org
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Size: 3125248 |
Author: Kiran |
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Description: tHIS DOCUMENT IS ABOUT IMPLEMENTATION OF FFT IN VHDL WITH A HIGH THROUGHPUT
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Size: 126976 |
Author: sam |
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Description: FPGA下用VHDL实现的基2 cooley-tukey的8位FFT算法,在quartus ii环境下验证成功。-Under FPGA with base 2 cooley-tukey of 8 FFT algorithm VHDL realize, in quartus ii environment successfully verified.
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Size: 7577600 |
Author: lht |
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Description: 基于fpga的fft变换,用ip核实现。用vhdl编写-Fpga based fft transform, use ip core implementation. Written in vhdl
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Size: 4431872 |
Author: 任天鹏 |
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Description: 用ip核实现fft。用vhdl编写。altera的fpga-Ip core implementation using fft. Written in vhdl
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Size: 5501952 |
Author: 任天鹏 |
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